The present invention relates to a plasma processing apparatus applied to microfabrication in semiconductor fabricating processes or the like and, more particularly, to a plasma processing apparatus provided with a holding stage on which a semiconductor wafer is to be placed.
With the trend toward high integration design of semiconductor devices becoming remarkable in recent years, ever-increasing miniaturization of circuit patterns has been demanded and dimensional fabrication accuracy required has been increasingly severe. Moreover, at the same time, it has become necessary to meet requirements for improved throughput and larger areas of workpieces to be treated and the temperature controllability of semiconductor wafers during processing has become very important.
For example, in an etching process that requires a high aspect ratio (fine and deep trenches), anisotropic etching is required and in order to realize this, a process in which etching is performed while protecting side walls with an organic polymer is adopted and, in this case, the generation of an organic polymer that provides protective films varies depending on temperature. If the temperature within a semiconductor wafer during etching processing is nonuniformly distributed, the degree of formation of side wall protecting films varies in the wafer plane, with the result that etching shape also may sometimes become nonuniform, thus posing a problem.
Also, there is a case where reaction products adhere to etched surfaces again, thereby lowering etching rates. The reaction products are apt to be distributed more at the center of a semiconductor wafer than near the outer periphery of the semiconductor wafer, with the result that the etching rate is lower at the center of the semiconductor wafer than near the outer periphery and, therefore, the etching shape within the semiconductor wafer plane deviates.
In order to improve this, it is effective to adopt a method by which the re-adhering of reaction products is suppressed by raising the temperature near the center of a wafer in comparison with the temperature near the outer periphery. Therefore, as described above, it is necessary to control the semiconductor wafer temperature during plasma etching so that it is uniform in the wafer plane or to cancel out the distribution of reaction products by intentionally raising the temperature in the plane of a semiconductor wafer at the center or near the outer periphery.
Incidentally, it is a general practice to realize the semiconductor wafer temperature control during processing by controlling the surface of an electrostatic chuck (a holding stage) on which the wafer to be treated is placed, and as a method of temperature control for such a semiconductor wafer during processing, a technique disclosed in JP-A-2000-216140 (prior art 1), for example, can be mentioned.
In this prior art 1, there is disclosed a structure such that a plurality of independent coolant flow paths capable of controlling the flow rate of coolant are provided within an electrostatic electrode block that constitutes a holding stage and the electrode block surface is coated with a dielectric film.
Furthermore, in JP-A-9-17770 (prior art 2) is disclosed a structure such that in order to control the in-plane temperature distribution of a semiconductor wafer, two systems of coolant flow path are provided on concentric circles in the interior of an electrostatic chuck, whereby a relatively low-temperature coolant is caused to circulate in an outer coolant flow path and a relatively high-temperature coolant is caused to circulate in an inner coolant flow path. In JP-A-845909 (prior art 3) is disclosed a sample bed (a holding stage) of such a structure that a metal electrode block is divided into portions, in each of which a coolant flow path or a heater is provided to perform temperature control.
In the above prior arts, consideration is not given to the flow of heat in an electrostatic chuck and there was a problem in positively realizing a clear temperature distribution.
For examples, in the prior arts 1 and 2, in order to realize a temperature distribution in which the temperature near the center of a semiconductor wafer during processing is set higher than the temperature near the outer periphery of the wafer, the temperature or flow rate of a coolant is controlled. However, a clear in-plane temperature distribution cannot be obtained because of the thermal conductivity of the electrode block and, at the same time, because coolant flow paths are adjacent to each other, the temperature is made uniform within the electrode block, making it further impossible to obtain a clear temperature distribution.
On the other hand, in the electrostatic chuck disclosed as the prior art 3, independent temperature control is possible within divided electrode blocks and in-plane temperature distribution control is accomplished. However, because there is a gap between the blocks, it is difficult to form dielectric films of thin film thickness with good reliability.
Also, in the prior art 1, the electrode is fixed by means of screws only in the circumferential part and, therefore, the electrode block is deformed in convex shape by the pressure of the coolant, with the result that in some cases it is impossible to uniformly adsorb the semiconductor wafer and an undesired temperature distribution is generated in the plane of the semiconductor wafer.